IBM says it has come up with a process that will make it easier to make 3D stacked chips, although can’t confirm when this technology might be ready.
Big Blue has been working with Japanese semiconductor outfit Tokyo Electron on a way to simplify the process of making 3D stacked chips. The pair say they have built a beta system in Albany, New York (presumably at the Thomas J Watson Research Center), where they will test how the process can be implemented into a full semiconductor manufacturing workflow to deliver a complete 3D chip stack.
Chip stacking is used mostly in products such as high-bandwidth memory, but IBM believes it has the potential to side-step the end of Moore’s Law by expanding the number of transistors that can fit in a given volume rather than in a flat area spread out on a single chip.
The end of Moore’s Law, as most Reg readers know, chiefly refers to the way manufacturing processes are potentially approaching the physical limits of silicon, with 2nm process nodes expected to come online within the next few years.
Manufacturing vertically stacked chips requires fragile silicon wafers to be attached to a carrier wafer during the production process. These carrier wafers can also be made of silicon, but mechanical force is needed to separate them after processing, which can damage the wafers and reduce yields, according to IBM. For this reason, glass is typically used, as it can be temporarily bonded to the production wafer and debonded using ultraviolet lasers.
IBM and Tokyo Electron say they have developed a new process that uses an infrared laser that can debond silicon, meaning that standard silicon wafers can be used as carriers instead of glass. This simplifies the production process by doing away with the need for glass, but is also claimed to have other advantages such as eliminating tool compatibility issues, reducing defects, and enabling inline testing of wafers.
The two companies have worked on this technology since 2018, as part of their collaboration on chip manufacturing that dates back more than 20 years. Tokyo Electron has largely been responsible for developing a new 300mm production unit capable of releasing and separating bonded silicon wafer pairs for volume manufacturing.
We asked IBM when this new process might actually be ready to deliver production 3D stacked chips, but they were not immediately able to respond. However, it seems likely that it will be at least several years before the test system translates into a usable commercial process, if at all. ®